mirror of
https://github.com/pentoo/pentoo-overlay
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capstone: remove radare2 patches, confirmed with @aquynh
This commit is contained in:
blshkv
parent
7c81c54f6e
commit
7a3adf65c1
8 changed files with 0 additions and 414 deletions
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@ -19,32 +19,3 @@ PDEPEND="python? ( >=dev-python/capstone-python-${PV} )"
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RDEPEND=""
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DEPEND="${RDEPEND}"
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#TODO: add java and ocaml bindings
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PATCHES=(
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# "${FILESDIR}/capstone-calloc.patch"
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# "${FILESDIR}/fix-m68k-oob.patch"
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# "${FILESDIR}/fix-underflow-tms.patch"
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"${FILESDIR}/fix-x86-16.patch"
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"${FILESDIR}/sparc-crash.patch"
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"${FILESDIR}/sstream-null.patch"
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)
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#src_configure() {
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# {
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# cat <<-EOF
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# # Gentoo overrides:
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# # verbose build
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# V = 1
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# # toolchain
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# AR = $(tc-getAR)
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# CC = $(tc-getCC)
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# RANLIB = $(tc-getRANLIB)
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# # toolchain flags
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# CFLAGS = ${CFLAGS}
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# LDFLAGS = ${LDFLAGS}
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# # libs
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# LIBDIRARCH = $(get_libdir)
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# EOF
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# } >> config.mk || die
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#}
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@ -1,60 +0,0 @@
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diff --git a/MCInst.c b/MCInst.c
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index cc062d00..3f75de3b 100644
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--- a/MCInst.c
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+++ b/MCInst.c
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@@ -16,15 +16,7 @@
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void MCInst_Init(MCInst *inst)
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{
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- inst->Opcode = 0;
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- inst->OpcodePub = 0;
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- inst->size = 0;
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- inst->has_imm = false;
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- inst->op1_size = 0;
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- inst->writeback = false;
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- inst->ac_idx = 0;
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- inst->popcode_adjust = 0;
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- inst->assembly[0] = '\0';
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+ memset (inst, 0, sizeof (MCInst));
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}
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void MCInst_clear(MCInst *inst)
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diff --git a/cs.c b/cs.c
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index 449b1da5..fe87a318 100644
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--- a/cs.c
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+++ b/cs.c
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@@ -641,7 +641,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64
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size_org = size;
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total_size = sizeof(cs_insn) * cache_size;
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- total = cs_mem_malloc(total_size);
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+ total = cs_mem_calloc(1, total_size);
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if (total == NULL) {
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// insufficient memory
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handle->errnum = CS_ERR_MEM;
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@@ -659,7 +659,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64
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if (handle->detail) {
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// allocate memory for @detail pointer
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- insn_cache->detail = cs_mem_malloc(sizeof(cs_detail));
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+ insn_cache->detail = cs_mem_calloc(1, sizeof(cs_detail));
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} else {
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insn_cache->detail = NULL;
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}
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@@ -747,6 +747,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64
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if (f == cache_size) {
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// full cache, so expand the cache to contain incoming insns
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cache_size = cache_size * 8 / 5; // * 1.6 ~ golden ratio
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+ unsigned int old_size = total_size;
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total_size += (sizeof(cs_insn) * cache_size);
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tmp = cs_mem_realloc(total, total_size);
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if (tmp == NULL) { // insufficient memory
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@@ -761,7 +762,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64
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handle->errnum = CS_ERR_MEM;
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return 0;
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}
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-
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+ memset (total + (sizeof(cs_insn) * old_size), 0, (total_size - old_size));
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total = tmp;
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// continue to fill in the cache after the last instruction
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insn_cache = (cs_insn *)((char *)total + sizeof(cs_insn) * c);
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@ -1,24 +0,0 @@
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diff --git a/arch/M68K/M68KInstPrinter.c b/arch/M68K/M68KInstPrinter.c
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index c545115..aec6a05 100644
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--- a/arch/M68K/M68KInstPrinter.c
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+++ b/arch/M68K/M68KInstPrinter.c
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@@ -28,7 +28,8 @@
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#ifndef CAPSTONE_DIET
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static const char* s_spacing = " ";
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-static const char* s_reg_names[] = {
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+#define S_REG_NAMES_COUNT 47
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+static const char* s_reg_names[S_REG_NAMES_COUNT] = {
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"invalid",
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"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
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"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
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@@ -326,6 +327,9 @@ const char* M68K_reg_name(csh handle, unsigned int reg)
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#ifdef CAPSTONE_DIET
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return NULL;
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#else
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+ if (reg >= S_REG_NAMES_COUNT) {
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+ return NULL;
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+ }
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return s_reg_names[(int)reg];
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#endif
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}
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@ -1,28 +0,0 @@
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diff --git a/arch/TMS320C64x/TMS320C64xInstPrinter.c b/arch/TMS320C64x/TMS320C64xInstPrinter.c
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index fa57893..d6e9896 100644
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--- a/arch/TMS320C64x/TMS320C64xInstPrinter.c
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+++ b/arch/TMS320C64x/TMS320C64xInstPrinter.c
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@@ -70,15 +70,14 @@ void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
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if((p != NULL) && (((p2 = strchr(p, '[')) != NULL) || ((p2 = strchr(p, '(')) != NULL))) {
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while((p2 > p) && ((*p2 != 'A') && (*p2 != 'B')))
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p2--;
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- if(p2 == p) {
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- strcpy(insn_asm, "Invalid!");
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- return;
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- } else {
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- if(*p2 == 'A')
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- strcpy(tmp, "1T");
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- else
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- strcpy(tmp, "2T");
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- }
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+ if(p2 <= p) {
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+ strcpy(insn_asm, "Invalid!");
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+ return;
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+ }
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+ if(*p2 == 'A')
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+ strcpy(tmp, "1T");
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+ else
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+ strcpy(tmp, "2T");
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} else {
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tmp[0] = '\0';
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}
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@ -1,30 +0,0 @@
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diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
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index 7e19b4e..062eef8 100644
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--- a/arch/X86/X86ATTInstPrinter.c
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+++ b/arch/X86/X86ATTInstPrinter.c
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@@ -576,6 +576,10 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
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if (MI->Opcode == X86_CALLpcrel16 || MI->Opcode == X86_JMP_2)
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imm = imm & 0xffff;
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+ if (MI->csh->mode == CS_MODE_16) {
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+ imm |= (MI->address >> 16) << 16;
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+ }
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+
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if (imm < 0) {
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SStream_concat(O, "0x%"PRIx64, imm);
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} else {
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diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c
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index c455725..eb60586 100644
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--- a/arch/X86/X86IntelInstPrinter.c
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+++ b/arch/X86/X86IntelInstPrinter.c
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@@ -756,6 +756,10 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
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if (MI->Opcode == X86_CALLpcrel16 || MI->Opcode == X86_JMP_2)
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imm = imm & 0xffff;
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+ if (MI->csh->mode == CS_MODE_16) {
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+ imm |= (MI->address >> 16) << 16;
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+ }
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+
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printImm(MI->csh->syntax, O, imm, true);
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if (MI->csh->detail) {
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@ -1,215 +0,0 @@
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From 711a9ee48751fcdd2826591df043e6867f425f0c Mon Sep 17 00:00:00 2001
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From: mrmacete <mrmacete@protonmail.ch>
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Date: Wed, 31 May 2017 09:27:08 +0200
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Subject: [PATCH] Add CS_MODE_MIPS2 to opt-in for COP3 instructions
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---
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arch/Mips/MipsDisassembler.c | 2 +-
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arch/Mips/MipsModule.c | 3 ++-
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bindings/java/capstone/Capstone.java | 1 +
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bindings/ocaml/capstone.ml | 1 +
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bindings/ocaml/ocaml.c | 22 ++++++++++++++--------
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bindings/python/capstone/__init__.py | 2 ++
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include/capstone/capstone.h | 1 +
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tests/test_mips.c | 23 +++++++++++++++++++----
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8 files changed, 41 insertions(+), 14 deletions(-)
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diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
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index 846115f72..dfc07eed3 100644
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--- a/arch/Mips/MipsDisassembler.c
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+++ b/arch/Mips/MipsDisassembler.c
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@@ -451,7 +451,7 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
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readInstruction32((unsigned char*)code, &Insn, isBigEndian, false);
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- if (((mode & CS_MODE_MIPS32) == 0) && ((mode & CS_MODE_MIPS3) == 0)) {
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+ if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) {
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// DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
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Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode);
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if (Result != MCDisassembler_Fail) {
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diff --git a/arch/Mips/MipsModule.c b/arch/Mips/MipsModule.c
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index 0b4a60f40..b74c27055 100644
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--- a/arch/Mips/MipsModule.c
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+++ b/arch/Mips/MipsModule.c
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@@ -15,7 +15,8 @@ static cs_err init(cs_struct *ud)
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// verify if requested mode is valid
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if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 |
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- CS_MODE_MICRO | CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN))
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+ CS_MODE_MICRO | CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN |
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+ CS_MODE_MIPS2 | CS_MODE_MIPS3))
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return CS_ERR_MODE;
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mri = cs_mem_malloc(sizeof(*mri));
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diff --git a/bindings/java/capstone/Capstone.java b/bindings/java/capstone/Capstone.java
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index 2d49f9121..19fbd8a08 100644
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--- a/bindings/java/capstone/Capstone.java
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+++ b/bindings/java/capstone/Capstone.java
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@@ -336,6 +336,7 @@ public NativeLong cs_disasm(NativeLong handle, byte[] code, NativeLong code_len,
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public static final int CS_MODE_MICRO = 1 << 4; // MicroMips mode (Mips arch)
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public static final int CS_MODE_MIPS3 = 1 << 5; // Mips III ISA
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public static final int CS_MODE_MIPS32R6 = 1 << 6; // Mips32r6 ISA
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+ public static final int CS_MODE_MIPS2 = 1 << 7; // Mips II ISA
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public static final int CS_MODE_BIG_ENDIAN = 1 << 31; // big-endian mode
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public static final int CS_MODE_V9 = 1 << 4; // SparcV9 mode (Sparc arch)
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public static final int CS_MODE_MIPS32 = CS_MODE_32; // Mips32 ISA
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diff --git a/bindings/ocaml/capstone.ml b/bindings/ocaml/capstone.ml
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index 6da4cba88..a81b90dd6 100644
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--- a/bindings/ocaml/capstone.ml
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+++ b/bindings/ocaml/capstone.ml
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@@ -35,6 +35,7 @@ type mode =
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| CS_MODE_MICRO (* MicroMips mode (MIPS architecture) *)
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| CS_MODE_MIPS3 (* Mips3 mode (MIPS architecture) *)
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| CS_MODE_MIPS32R6 (* Mips32-R6 mode (MIPS architecture) *)
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+ | CS_MODE_MIPS2 (* Mips2 mode (MIPS architecture) *)
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| CS_MODE_V9 (* SparcV9 mode (Sparc architecture) *)
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| CS_MODE_BIG_ENDIAN (* big-endian mode *)
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| CS_MODE_MIPS32 (* Mips32 mode (for Mips) *)
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diff --git a/bindings/ocaml/ocaml.c b/bindings/ocaml/ocaml.c
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index 038daf8b7..4e2644162 100644
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--- a/bindings/ocaml/ocaml.c
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+++ b/bindings/ocaml/ocaml.c
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@@ -700,18 +700,21 @@ CAMLprim value ocaml_cs_disasm(value _arch, value _mode, value _code, value _add
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mode |= CS_MODE_MIPS32R6;
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break;
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case 11:
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- mode |= CS_MODE_V9;
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+ mode |= CS_MODE_MIPS2;
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break;
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case 12:
|
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- mode |= CS_MODE_BIG_ENDIAN;
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+ mode |= CS_MODE_V9;
|
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break;
|
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case 13:
|
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- mode |= CS_MODE_MIPS32;
|
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+ mode |= CS_MODE_BIG_ENDIAN;
|
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break;
|
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case 14:
|
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- mode |= CS_MODE_MIPS64;
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+ mode |= CS_MODE_MIPS32;
|
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break;
|
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case 15:
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+ mode |= CS_MODE_MIPS64;
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+ break;
|
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+ case 16:
|
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mode |= CS_MODE_QPX;
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break;
|
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default:
|
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@@ -831,18 +834,21 @@ CAMLprim value ocaml_open(value _arch, value _mode)
|
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mode |= CS_MODE_MIPS32R6;
|
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break;
|
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case 11:
|
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- mode |= CS_MODE_V9;
|
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+ mode |= CS_MODE_MIPS2;
|
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break;
|
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case 12:
|
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- mode |= CS_MODE_BIG_ENDIAN;
|
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+ mode |= CS_MODE_V9;
|
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break;
|
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case 13:
|
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- mode |= CS_MODE_MIPS32;
|
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+ mode |= CS_MODE_BIG_ENDIAN;
|
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break;
|
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case 14:
|
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- mode |= CS_MODE_MIPS64;
|
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+ mode |= CS_MODE_MIPS32;
|
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break;
|
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case 15:
|
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+ mode |= CS_MODE_MIPS64;
|
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+ break;
|
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+ case 16:
|
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mode |= CS_MODE_QPX;
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break;
|
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default:
|
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diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
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index 592b0eae6..a7c1453ab 100644
|
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--- a/bindings/python/capstone/__init__.py
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+++ b/bindings/python/capstone/__init__.py
|
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@@ -46,6 +46,7 @@
|
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'CS_MODE_MICRO',
|
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'CS_MODE_MIPS3',
|
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'CS_MODE_MIPS32R6',
|
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+ 'CS_MODE_MIPS2',
|
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'CS_MODE_V8',
|
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'CS_MODE_V9',
|
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'CS_MODE_QPX',
|
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@@ -151,6 +152,7 @@
|
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CS_MODE_MICRO = (1 << 4) # MicroMips mode (MIPS architecture)
|
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CS_MODE_MIPS3 = (1 << 5) # Mips III ISA
|
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CS_MODE_MIPS32R6 = (1 << 6) # Mips32r6 ISA
|
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+CS_MODE_MIPS2 = (1 << 7) # Mips II ISA
|
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CS_MODE_V9 = (1 << 4) # Sparc V9 mode (for Sparc)
|
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CS_MODE_QPX = (1 << 4) # Quad Processing eXtensions mode (PPC)
|
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CS_MODE_M68K_000 = (1 << 1) # M68K 68000 mode
|
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diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h
|
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index fc06307cb..e6a90b5fd 100644
|
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--- a/include/capstone/capstone.h
|
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+++ b/include/capstone/capstone.h
|
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@@ -109,6 +109,7 @@ typedef enum cs_mode {
|
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CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS)
|
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CS_MODE_MIPS3 = 1 << 5, // Mips III ISA
|
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CS_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA
|
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+ CS_MODE_MIPS2 = 1 << 7, // Mips II ISA
|
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CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc)
|
||||
CS_MODE_QPX = 1 << 4, // Quad Processing eXtensions mode (PPC)
|
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CS_MODE_M68K_000 = 1 << 1, // M68K 68000 mode
|
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diff --git a/tests/test_mips.c b/tests/test_mips.c
|
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index 9e2927c2b..2a7948b8c 100644
|
||||
--- a/tests/test_mips.c
|
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+++ b/tests/test_mips.c
|
||||
@@ -82,36 +82,51 @@ static void test()
|
||||
#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
|
||||
#define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
|
||||
#define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0"
|
||||
+#define MIPS_64SD "\x70\x00\xb2\xff"
|
||||
|
||||
struct platform platforms[] = {
|
||||
{
|
||||
CS_ARCH_MIPS,
|
||||
- (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
|
||||
+ (cs_mode)(CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN),
|
||||
(unsigned char *)MIPS_CODE,
|
||||
sizeof(MIPS_CODE) - 1,
|
||||
"MIPS-32 (Big-endian)"
|
||||
},
|
||||
{
|
||||
CS_ARCH_MIPS,
|
||||
- (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
|
||||
+ (cs_mode)(CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN),
|
||||
(unsigned char *)MIPS_CODE2,
|
||||
sizeof(MIPS_CODE2) - 1,
|
||||
"MIPS-64-EL (Little-endian)"
|
||||
},
|
||||
{
|
||||
CS_ARCH_MIPS,
|
||||
- (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
|
||||
+ (cs_mode)(CS_MODE_MIPS32R6 | CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
|
||||
(unsigned char*)MIPS_32R6M,
|
||||
sizeof(MIPS_32R6M) - 1,
|
||||
"MIPS-32R6 | Micro (Big-endian)"
|
||||
},
|
||||
{
|
||||
CS_ARCH_MIPS,
|
||||
- (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
|
||||
+ (cs_mode)(CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN),
|
||||
(unsigned char*)MIPS_32R6,
|
||||
sizeof(MIPS_32R6) - 1,
|
||||
"MIPS-32R6 (Big-endian)"
|
||||
},
|
||||
+ {
|
||||
+ CS_ARCH_MIPS,
|
||||
+ (cs_mode)(CS_MODE_MIPS64 | CS_MODE_MIPS2 | CS_MODE_LITTLE_ENDIAN),
|
||||
+ (unsigned char *)MIPS_64SD,
|
||||
+ sizeof(MIPS_64SD) - 1,
|
||||
+ "MIPS-64-EL + Mips II (Little-endian)"
|
||||
+ },
|
||||
+ {
|
||||
+ CS_ARCH_MIPS,
|
||||
+ (cs_mode)(CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN),
|
||||
+ (unsigned char *)MIPS_64SD,
|
||||
+ sizeof(MIPS_64SD) - 1,
|
||||
+ "MIPS-64-EL (Little-endian)"
|
||||
+ },
|
||||
};
|
||||
|
||||
uint64_t address = 0x1000;
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
diff --git a/arch/Sparc/SparcGenAsmWriter.inc b/arch/Sparc/SparcGenAsmWriter.inc
|
||||
index 9ed9760..9694d05 100644
|
||||
--- a/arch/Sparc/SparcGenAsmWriter.inc
|
||||
+++ b/arch/Sparc/SparcGenAsmWriter.inc
|
||||
@@ -1202,6 +1202,9 @@ static char *getRegisterName(unsigned RegNo)
|
||||
//for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
|
||||
// printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
|
||||
//printf("*************************\n");
|
||||
+if (RegNo < 1 || RegNo > sizeof (RegAsmOffset) / sizeof (*RegAsmOffset)) {
|
||||
+ return NULL;
|
||||
+}
|
||||
return AsmStrs+RegAsmOffset[RegNo-1];
|
||||
#else
|
||||
return NULL;
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
diff --git a/SStream.c b/SStream.c
|
||||
index c90cf1a..1686d5d 100644
|
||||
--- a/SStream.c
|
||||
+++ b/SStream.c
|
||||
@@ -28,6 +28,9 @@ void SStream_Init(SStream *ss)
|
||||
void SStream_concat0(SStream *ss, char *s)
|
||||
{
|
||||
#ifndef CAPSTONE_DIET
|
||||
+ if (!ss || !s) {
|
||||
+ return;
|
||||
+ }
|
||||
unsigned int len = (unsigned int) strlen(s);
|
||||
|
||||
memcpy(ss->buffer + ss->index, s, len);
|
||||
Loading…
Reference in a new issue